commit 97f430c5d9f37a44d786250900bef309d9259366 Author: gael.pongnot Date: Mon Sep 12 09:41:33 2022 +0200 Initial commit diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..ab1acd6 --- /dev/null +++ b/.cproject @@ -0,0 +1,223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_2="LPC80x_32.cfx" property_3="NXP" property_4="LPC804" property_count="5" version="100300"/> +<infoList vendor="NXP"> +<info chip="LPC804" flash_driver="LPC80x_32.cfx" match_id="0x0" name="LPC804" stub="crt_emu_cm3_gen"> +<chip> +<name>LPC804</name> +<family>LPC80x</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x7f80"/> +<memoryInstance derived_from="RAM" id="RamLoc4" location="0x10000000" size="0x1000"/> +</chip> +<processor> +<name gcc_name="cortex-m0">Cortex-M0</name> +<family>Cortex-M</family> +</processor> +</info> +</infoList> +</TargetConfig> + + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..95bd7c3 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +/flash +*.launch \ No newline at end of file diff --git a/.project b/.project new file mode 100644 index 0000000..1e193a3 --- /dev/null +++ b/.project @@ -0,0 +1,28 @@ + + + Projet_e-paper + + + peripherals_lib + utilities_lib + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..d8797e1 --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/docs/README.txt b/docs/README.txt new file mode 100644 index 0000000..0b9fbc1 --- /dev/null +++ b/docs/README.txt @@ -0,0 +1,123 @@ +${ProjName}: +UART0_Terminal + + +Intended purpose: +To demonstrate the configuration and use of the USART module, in asynchronous +mode, while communicating with a terminal emulator. + + +Functional description: +* In this example UART0 communicates with a terminal emulator running on the PC, via a + USB-to-RS232 breakout cable or via the NXP LPC11Uxx VCOM serial port. +* The user is prompted to enter a string (not to exceed 32 characters), terminated by [Enter]. +* Each character that is entered is echoed back to the terminal by the UART0 + ISR, and the characters are stored in an array for future use. +* When the user types [Enter], a NUL character is appended to the array, and + a handshake flag is set by the ISR for the main routine. +* Upon seeing the handshake flag, the main routine prints the stored string to + the terminal, and the process repeats. + + +External connections: +* To use the NXP LPC11Uxx VCOM Serial Port: + 1. No external connections are necessary. + 2. The Max board must have the necessary solder-bump jumper modifications: + A. For LPC812 Max board, short pins 1 and 2 of both SJ1 and SJ4 + B. For LPC824 Max board, short pins 2 and 3 of SJ9 + C. For LPC845 Max board, no modification is needed. + C. For LPC802 LPCXpresso board, no modification is needed. + C. For LPC804 LPCXpresso board, no modification is needed. + 3. The terminal emulator can then be connected to the NXP LPC11Uxx VCOM serial port which + enumerates when the board is connected. It appears something like this: + COM13: NXP LPC11Uxx VCOM serial port (COM13) + +* To use a USB-to-RS232 breakout cable: + 1. There are three external connections necessary: RXD and TXD based on the SWM + settings, plus a ground connection. The RXD and TXD pins can be chosen in chip_setup.h. + The defaults are as follows: + P0.25 = U0_TXD = breakout cable RXD + P0.24 = U0_RXD = breakout cable TXD + Board GND = breakout cable GND + + + +Notes on the baud rate and FRG: +* The BRG and FRG settings are calculated in two steps, as follows: + // For asynchronous mode (UART mode) the formula is: + // (BRG + 1) * (1 + (m/256)) * (16 * baudrate Hz.) = FRG_in Hz. + // We proceed in 2 steps. + // Step 1: Let m = 0, and round (down) to the nearest integer value of BRG for the desired baudrate. + // Step 2: Plug in the BRG from step 1, and find the nearest integer value of m, (for the FRG fractional part). + // + // Step 1 (with m = 0) + // BRG = ((FRG_in Hz.) / (16 * baudrate Hz.)) - 1 + // = (30,000,000/(16 * 9600)) - 1 + // = 194.3 + // = 194 (rounded) + // + // Step 2. + // m = 256 * [-1 + {(FRG_in Hz.) / (16 * baudrate Hz.)(BRG + 1)}] + // = 256 * [-1 + {(30,000,000) / (16*9600)(195)}] + // = 0.002 + // = 0 (rounded) + + +Program Flow: +* This example runs with: + system_ahb_clk = 15 MHz. (main_clk = 15 MHz. FRO direct output) + UART0CLK = 15 MHz. (FRG0CLKSEL = main_clk, FCLKSEL0 = frg0clk) + See chip_setup.h and SystemInit() + +* main() routine + 1. Clocks to USART0 and the SWM are enabled. + + 2. The SWM is configured as per above. + + 3. The UARTCLKDIV and the FRG (both in SYSCON) are configured as per above + (for 9600 b.p.s.). + + 4. USART0 is given a peripheral reset. + + 5. USART0 BRG is configured as per above (for 9600 b.p.s.). + + 6. USART0 CFG register is configured for: + 8 data bits + no parity + one stop bit + no flow control + asynchronous mode + no loop-back + + 7. USART0 CTL register is configured for: + no continuous break + no address detect + no Tx disable + no CC + no CLRCC + + 8. USART0 Rx Ready interrupt is enabled, and code execution enters the main while(1) + loop. + + 9. The user is prompted to enter a string, and each character is echoed by the + ISR back to the terminal until the NUL terminator is encountered. + + 10. When the NUL terminator is encountered, the ISR sets a handshake flag for + main, which prints the entire received string to the terminal, and the process repeats. + + +This example runs from Flash. + + +To run this code: + 1. Build + 2. Program memory, then reset target + or + 2. Debug + 3. Run or Go + +Note: It may be necessary to power-cycle the board in order to regain control of the reset button after programming. + + + + diff --git a/inc/chip_setup.h b/inc/chip_setup.h new file mode 100644 index 0000000..fdf7373 --- /dev/null +++ b/inc/chip_setup.h @@ -0,0 +1,66 @@ +#include "board.h" + + +// +// The following parameters need to be defined for each project's inital clock setup (used in system.c)) +// +#define FRO_FREQ_VAL 2 // 0 = 18 MHz + // 1 = 24 MHz (reset value) + // 2 = 30 MHz + +#define MAINCLKSEL_VAL 0 // 00 = fro (reset value) + // 01 = external_clk + // 10 = lposc_clk + // 11 = fro_div + +#define SYSAHBCLKDIV_VAL 1 // 0x00 = system_ahb_clk disabled (use with caution) + // 0x01 = divide_by_1 (reset value) + // 0x02 = divide_by_2 + // 0xFF = divide_by_255 + +#define CLKIN_CLK_VAL 12000000 // External Clock (CLKIN) frequency [Hz] must be in the range of 1 MHz to 25 MHz + +#define EXT_CLOCK_FORCE_ENABLE 0 // Force config. and enable of external_clk for use by other than main_clk + // 0 = external_clk will be configured and enabled only if needed by main_clk or sys_pll0_clk. + // 1 = external_clk will be configured and enabled (available for other, e.g. clock out). + +// End of clocks configuration section + + + + + + + + + + +// +// The following parameters need to be defined for projects that use the debug UART (used in serial.c) +// +#define DBGUART 0 // Choose the index for the debug UART (0 for UART0, 1 for UART1, etc.) +#define DBGBAUDRATE 9600 // Choose the baud rate for the debug UART +#define USE_VCOM_PORT 1 // '1' to use VCOM serial port, '0' to use user-defined port pins for debug UART + +#if (USE_VCOM_PORT == 1) + #define DBGTXPIN TARGET_TX // For VCOM serial port (see board.h) + #define DBGRXPIN TARGET_RX // For VCOM serial port (see board.h) +#else + #define DBGTXPIN P0_15 // Use with USB-to-RS232 break-out cable (choose your own favorite TxD pin) + #define DBGRXPIN P0_14 // Use with USB-to-RS232 break-out cable (choose your own favorite RxD pin) +#endif + +// +// The following are so the debug UART is selectable from any UART on the device (used in Serial.c) +// +#define __CONCAT(x,y,z) x##y##z +#define __XCONCAT(x,y,z) __CONCAT(x,y,z) + +#define INDEX DBGUART +#define pDBGU __XCONCAT(LPC_USART,INDEX,) +#define DBGU __XCONCAT(UART,INDEX,) +#define DBGUTXD __XCONCAT(U,INDEX,_TXD) +#define DBGURXD __XCONCAT(U,INDEX,_RXD) +#define DBGURST __XCONCAT(UART,INDEX,_RST_N) +#define DBGUIRQ __XCONCAT(UART,INDEX,_IRQn) + diff --git a/inc/lib_ENS_II1_lcd.h b/inc/lib_ENS_II1_lcd.h new file mode 100644 index 0000000..9134c1a --- /dev/null +++ b/inc/lib_ENS_II1_lcd.h @@ -0,0 +1,23 @@ +/* + * lib_ENS_II1_lcd.h + * + * Created on: 9 oct. 2018 + * Modified on sept. 2019 + * Author: juton + */ + +#ifndef LIB_ENS_II1_LCD_H_ +#define LIB_ENS_II1_LCD_H_ + +//definitions pour I2C +#define I2CBAUD 100000 +#define LCD_ADDR 0x7C +#define BUFSIZE 5 + +void init_lcd(void); +void lcd_puts(); +void lcd_putc(char c); +void lcd_gohome(); +void lcd_position(char ligne, char colonne); + +#endif /* LIB_ENS_II1_LCD_H_ */ diff --git a/inc/lib_epaper_2in9.h b/inc/lib_epaper_2in9.h new file mode 100644 index 0000000..e69de29 diff --git a/src/MCUXpresso_cr_startup.c b/src/MCUXpresso_cr_startup.c new file mode 100644 index 0000000..e556c51 --- /dev/null +++ b/src/MCUXpresso_cr_startup.c @@ -0,0 +1,355 @@ +//***************************************************************************** +// LPC84x Microcontroller Startup code for use with MCUXpresso IDE +// +// Version : 170111 +//***************************************************************************** +// +// Copyright(C) NXP Semiconductors, 2017 +// All rights reserved. +// +// Software that is described herein is for illustrative purposes only +// which provides customers with programming information regarding the +// LPC products. This software is supplied "AS IS" without any warranties of +// any kind, and NXP Semiconductors and its licensor disclaim any and +// all warranties, express or implied, including all implied warranties of +// merchantability, fitness for a particular purpose and non-infringement of +// intellectual property rights. NXP Semiconductors assumes no responsibility +// or liability for the use of the software, conveys no license or rights under any +// patent, copyright, mask work right, or any other intellectual property rights in +// or to any products. NXP Semiconductors reserves the right to make changes +// in the software without notification. NXP Semiconductors also makes no +// representation or warranty that such application will be suitable for the +// specified use without further testing or modification. +// +// Permission to use, copy, modify, and distribute this software and its +// documentation is hereby granted, under NXP Semiconductors' and its +// licensor's relevant copyrights in the software, without fee, provided that it +// is used in conjunction with NXP Semiconductors microcontrollers. This +// copyright, permission, and disclaimer notice must appear in all copies of +// this code. +//***************************************************************************** + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) +// Declaration of external SystemInit function +extern void SystemInit(void); +#endif + +//***************************************************************************** +// Patch the AEABI integer divide functions to use MCU's romdivide library +#ifdef __USE_ROMDIVIDE +// Location in memory that holds the address of the ROM Driver table +#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x0F001FF8)) +// Variables to store addresses of idiv and udiv functions within MCU ROM +unsigned int *pDivRom_idiv; +unsigned int *pDivRom_uidiv; +#endif + +//***************************************************************************** +// +// Forward declaration of the default handlers. These are aliased. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions +// +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// +// Forward declaration of the specific IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the application +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +// +//***************************************************************************** +void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler); +void DAC0_IRQHandler(void) ALIAS(IntDefaultHandler); +void UART0_IRQHandler(void) ALIAS(IntDefaultHandler); +void UART1_IRQHandler(void) ALIAS(IntDefaultHandler); +void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler); +void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler); +void MRT_IRQHandler(void) ALIAS(IntDefaultHandler); +void CMP_IRQHandler(void) ALIAS(IntDefaultHandler); +void WDT_IRQHandler(void) ALIAS(IntDefaultHandler); +void BOD_IRQHandler(void) ALIAS(IntDefaultHandler); +void FLASH_IRQHandler(void) ALIAS(IntDefaultHandler); +void WKT_IRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_OVR_IRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT0_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT1_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT2_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT3_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT4_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT5_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT6_IRQHandler(void) ALIAS(IntDefaultHandler); +void PININT7_IRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +// +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#else +extern int main(void); +#endif +//***************************************************************************** +// +// External declaration for the pointer to the stack top from the Linker Script +// +//***************************************************************************** +extern void _vStackTop(void); + +//***************************************************************************** +// +// External declaration for LPC MCU vector table checksum from Linker Script +// +//***************************************************************************** +WEAK extern void __valid_user_code_checksum(); + +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// +// The vector table. +// This relies on the linker script to place at correct location in memory. +// +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +__attribute__ ((used,section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM0plus + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + __valid_user_code_checksum, // LPC MCU Checksum + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + 0, // Reserved + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - LPC80x + SPI0_IRQHandler, // 0 - SPI0 + 0, // 1 - Reserved + DAC0_IRQHandler, // 2 - DAC0 + UART0_IRQHandler, // 3 - UART0 + UART1_IRQHandler, // 4 - UART1 + 0, // 5 - Reserved + 0, // 6 - Reserved + I2C1_IRQHandler, // 7 - I2C1 + I2C0_IRQHandler, // 8 - I2C0 + 0, // 9 - Reserved + MRT_IRQHandler, // 10 - Multi-rate timer + CMP_IRQHandler, // 11 - Analog comparator / Cap Touch + WDT_IRQHandler, // 12 - Windowed watchdog timer + BOD_IRQHandler, // 13 - BOD + FLASH_IRQHandler, // 14 - FLASH + WKT_IRQHandler, // 15 - Self wake-up timer + ADC_SEQA_IRQHandler, // 16 - ADC seq A + ADC_SEQB_IRQHandler, // 17 - ADC_seq B + ADC_THCMP_IRQHandler, // 18 - ADC threshold compare + ADC_OVR_IRQHandler, // 19 - ADC overrun + 0, // 20 - Reserved + 0, // 21 - Reserved + 0, // 22 - Reserved + CTIMER0_IRQHandler, // 23 - Timer 0 + PININT0_IRQHandler, // 24 - PININT0 + PININT1_IRQHandler, // 25 - PININT1 + PININT2_IRQHandler, // 26 - PININT2 + PININT3_IRQHandler, // 27 - PININT3 + PININT4_IRQHandler, // 28 - PININT4 + PININT5_IRQHandler, // 29 - PININT5 + PININT6_IRQHandler, // 30 - PININT6 + PININT7_IRQHandler // 31 - PININT7 +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void +ResetISR(void) { + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + // Patch the AEABI integer divide functions to use MCU's romdivide library +#ifdef __USE_ROMDIVIDE + // Get address of Integer division routines function table in ROM + unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4]; + // Get addresses of integer divide routines in ROM + // These address are then used by the code in aeabi_romdiv_patch.s + pDivRom_idiv = (unsigned int *)div_ptr[0]; + pDivRom_uidiv = (unsigned int *)div_ptr[1]; +#endif + +#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) + SystemInit(); +#endif + +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main() ; +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void NMI_Handler(void) +{ while(1) {} +} + +__attribute__ ((section(".after_vectors"))) +void HardFault_Handler(void) +{ while(1) {} +} + +__attribute__ ((section(".after_vectors"))) +void SVC_Handler(void) +{ while(1) {} +} + +__attribute__ ((section(".after_vectors"))) +void PendSV_Handler(void) +{ while(1) {} +} + +__attribute__ ((section(".after_vectors"))) +void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +// +//***************************************************************************** +__attribute__ ((section(".after_vectors"))) +void IntDefaultHandler(void) +{ while(1) {} +} diff --git a/src/MCUXpresso_crp.c b/src/MCUXpresso_crp.c new file mode 100644 index 0000000..5abed58 --- /dev/null +++ b/src/MCUXpresso_crp.c @@ -0,0 +1,38 @@ +//***************************************************************************** +// crp.c +// +// Source file to create CRP word expected by LPCXpresso IDE linker +//***************************************************************************** +// +// Copyright(C) NXP Semiconductors, 2013 +// All rights reserved. +// +// Software that is described herein is for illustrative purposes only +// which provides customers with programming information regarding the +// LPC products. This software is supplied "AS IS" without any warranties of +// any kind, and NXP Semiconductors and its licensor disclaim any and +// all warranties, express or implied, including all implied warranties of +// merchantability, fitness for a particular purpose and non-infringement of +// intellectual property rights. NXP Semiconductors assumes no responsibility +// or liability for the use of the software, conveys no license or rights under any +// patent, copyright, mask work right, or any other intellectual property rights in +// or to any products. NXP Semiconductors reserves the right to make changes +// in the software without notification. NXP Semiconductors also makes no +// representation or warranty that such application will be suitable for the +// specified use without further testing or modification. +// +// Permission to use, copy, modify, and distribute this software and its +// documentation is hereby granted, under NXP Semiconductors' and its +// licensor's relevant copyrights in the software, without fee, provided that it +// is used in conjunction with NXP Semiconductors microcontrollers. This +// copyright, permission, and disclaimer notice must appear in all copies of +// this code. +//***************************************************************************** + +#if defined (__CODE_RED) +#include +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +__CRP const unsigned int CRP_WORD = CRP_NO_CRP ; +#endif diff --git a/src/MCUXpresso_mtb.c b/src/MCUXpresso_mtb.c new file mode 100644 index 0000000..4a65389 --- /dev/null +++ b/src/MCUXpresso_mtb.c @@ -0,0 +1,86 @@ +//***************************************************************************** +// +--+ +// | ++----+ +// +-++ | +// | | +// +-+--+ | +// | +--+--+ +// +----+ Copyright (c) 2013 Code Red Technologies Ltd. +// +// mtb.c +// +// Optionally defines an array to be used as a buffer for Micro Trace +// Buffer (MTB) instruction trace on Cortex-M0+ parts +// +// Version : 130502 +// +// Software License Agreement +// +// The software is owned by Code Red Technologies and/or its suppliers, and is +// protected under applicable copyright laws. All rights are reserved. Any +// use in violation of the foregoing restrictions may subject the user to criminal +// sanctions under applicable laws, as well as to civil liability for the breach +// of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT +// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH +// CODE RED TECHNOLOGIES LTD. +// +//***************************************************************************** + +/******************************************************************* + * Symbols controlling behavior of this code... + * + * __MTB_DISABLE + * If this symbol is defined, then the buffer array for the MTB + * will not be created. + * + * __MTB_BUFFER_SIZE + * Symbol specifying the sizer of the buffer array for the MTB. + * This must be a power of 2 in size, and fit into the available + * RAM. The MTB buffer will also be aligned to its 'size' + * boundary and be placed at the start of a RAM bank (which + * should ensure minimal or zero padding due to alignment). + * + * __MTB_RAM_BANK + * Allows MTB Buffer to be placed into specific RAM bank. When + * this is not defined, the "default" (first if there are + * several) RAM bank is used. + *******************************************************************/ + +// Ignore with none Code Red tools +#if defined (__CODE_RED) + +// Allow MTB to be removed by setting a define (via command line) +#if !defined (__MTB_DISABLE) + + // Allow for MTB buffer size being set by define set via command line + // Otherwise provide small default buffer + #if !defined (__MTB_BUFFER_SIZE) + #define __MTB_BUFFER_SIZE 128 + #endif + + // Check that buffer size requested is >0 bytes in size + #if (__MTB_BUFFER_SIZE > 0) + // Pull in MTB related macros + #include + + // Check if MYTB buffer is to be placed in specific RAM bank + #if defined(__MTB_RAM_BANK) + // Place MTB buffer into explicit bank of RAM + __CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK); + #else + // Place MTB buffer into 'default' bank of RAM + __CR_MTB_BUFFER(__MTB_BUFFER_SIZE); + + #endif // defined(__MTB_RAM_BANK) + + #endif // (__MTB_BUFFER_SIZE > 0) + +#endif // !defined (__MTB_DISABLE) + +#endif // defined (__CODE_RED) + diff --git a/src/lib_ENS_II1_lcd.c b/src/lib_ENS_II1_lcd.c new file mode 100644 index 0000000..d891415 --- /dev/null +++ b/src/lib_ENS_II1_lcd.c @@ -0,0 +1,155 @@ +/* + * lib_ENS_II1_lcd.c + * + * Created on: 9 oct. 2018 + * Modified on sept 2019 + * Author: juton + */ + +#include +#include "fro.h" +#include "rom_api.h" +#include "syscon.h" +#include "swm.h" +#include "i2c.h" +#include "lib_ENS_II1_lcd.h" + +void init_lcd(void){ + + uint32_t i; + uint8_t I2CMasterBuffer[BUFSIZE]; + uint32_t I2CWriteLength; + + // Provide main_clk as function clock to I2C0 + LPC_SYSCON->I2C0CLKSEL = FCLKSEL_MAIN_CLK; + + LPC_SYSCON->SYSAHBCLKCTRL0 |= I2C0|SWM; + + //configuration des pins 7 (SDA) et 14 (SCL) en open_drain + LPC_IOCON->PIO0_7 = 0x000004A0; + LPC_IOCON->PIO0_14 = 0x000004A0; + + //assignation des pins 7 à SDA et 14 à SCL + LPC_SWM->PINASSIGN5 = 0xFFFF0E07; + + // Give I2C0 a reset + LPC_SYSCON->PRESETCTRL0 &= (I2C0_RST_N); + LPC_SYSCON->PRESETCTRL0 |= ~(I2C0_RST_N); + + //horloge I2c + LPC_I2C0->DIV = 1; + LPC_I2C0->CFG = CFG_MSTENA; + + for(i=0;i<8000;i++); + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CWriteLength = 1; + I2CMasterBuffer[0] = LCD_ADDR; + I2CMasterBuffer[1] = 0x00; + I2CMasterBuffer[2] = 0x38; /* configuration value, no change from default */ + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CWriteLength = 2; + I2CMasterBuffer[0] = LCD_ADDR; + I2CMasterBuffer[1] = 0x00; + I2CMasterBuffer[2] = 0x39; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x14; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x74; //contrast + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x54; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x6F; //follower + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x0E; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x01; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x06; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); + + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CMasterBuffer[2] = 0x02; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); +} + +void lcd_puts(char* text_input) +{ + uint8_t I2CMasterBuffer[BUFSIZE]; + uint32_t I2CWriteLength; + int i=0; + while(text_input[i]!=0) + { + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CWriteLength = 2; + I2CMasterBuffer[0] = LCD_ADDR; + I2CMasterBuffer[1] = 0x40; + I2CMasterBuffer[2] = text_input[i]; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + i++; + } +} + +void lcd_putc(char c) +{ + uint8_t I2CMasterBuffer[BUFSIZE]; + uint32_t I2CWriteLength; + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CWriteLength = 2; + I2CMasterBuffer[0] = LCD_ADDR; + I2CMasterBuffer[1] = 0x40; + I2CMasterBuffer[2] = c; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); +} + +void lcd_gohome(void){ + uint8_t I2CMasterBuffer[BUFSIZE]; + uint32_t I2CWriteLength,i; + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CWriteLength = 2; + I2CMasterBuffer[0] = LCD_ADDR; + I2CMasterBuffer[1] = 0x0; + I2CMasterBuffer[2] = 0x02; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); + for(i=0;i<8000;i++); +} + +void lcd_position(char ligne, char colonne){ + uint8_t I2CMasterBuffer[BUFSIZE]; + uint32_t I2CWriteLength; + char cmd; + if (ligne > 1) ligne=1; + if (colonne >16) colonne = 16; + cmd = 0x80+(ligne*0x40)+colonne; + WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle + I2CWriteLength = 2; + I2CMasterBuffer[0] = LCD_ADDR; + I2CMasterBuffer[1] = 0x0; + I2CMasterBuffer[2] = cmd; + I2CmasterWrite( I2CMasterBuffer, I2CWriteLength ); +} diff --git a/src/lib_epaper_2in9.c b/src/lib_epaper_2in9.c new file mode 100644 index 0000000..e69de29 diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..5208822 --- /dev/null +++ b/src/main.c @@ -0,0 +1,65 @@ +#include "LPC8xx.h" +#include "syscon.h" +#include "swm.h" +#include "spi.h" +#include "uart.h" +#include "utilities.h" +#include "chip_setup.h" +#include "lib_ENS_II1_lcd.h" + + +#define SPIBAUD 115200 +#define SCK_PIN P0_19 +#define MOSI_PIN P0_18 +#define SSEL_PIN P0_21 + +// +// Main routine +// +int main(void) { + + // Enable clocks to relevant peripherals + LPC_SYSCON->SYSAHBCLKCTRL[0] |= (SPI0|SWM); + + // Configure the SWM (see peripherals_lib and swm.h) + ConfigSWM(SPI0_SCK, SCK_PIN); + ConfigSWM(SPI0_MOSI, MOSI_PIN); + ConfigSWM(SPI0_SSEL0, SSEL_PIN); + + // Give SPI0 a reset + LPC_SYSCON->PRESETCTRL[0] &= (SPI0_RST_N); + LPC_SYSCON->PRESETCTRL[0] |= ~(SPI0_RST_N); + + // Enable main_clk as function clock to SPI + LPC_SYSCON->SPI0CLKSEL = FCLKSEL_MAIN_CLK; + + // Get main_clk frequency + SystemCoreClockUpdate(); + + // Configure the SPI master's clock divider (value written to DIV divides by value+1) + LPC_SPI0->DIV = (main_clk/SPIBAUD) - 1; + + // Configure the CFG register: + // Enable=true, master, no LSB first, CPHA=0, CPOL=0, no loop-back, SSEL active low + LPC_SPI0->CFG = SPI_CFG_ENABLE | SPI_CFG_MASTER; + + // Configure the SPI delay register (DLY) + // Pre-delay = 0 clocks, post-delay = 0 clocks, frame-delay = 0 clocks, transfer-delay = 0 clocks + LPC_SPI0->DLY = 0x0000; + + // Configure the SPI control register + // Master: End-of-frame true, End-of-transfer true, RXIGNORE true, LEN 8 bits. + LPC_SPI0->TXCTL = SPI_CTL_EOF | SPI_CTL_EOT | SPI_CTL_RXIGNORE | SPI_CTL_LEN(8); + + // Init LCD Screen + init_lcd(); + lcd_puts("Test e-paper"); + lcd_position(1, 0); + lcd_puts("Init ok"); + + while(1) { + + }; + +} // end of main + diff --git a/src/system.c b/src/system.c new file mode 100644 index 0000000..5777059 --- /dev/null +++ b/src/system.c @@ -0,0 +1,212 @@ +/**************************************************************************//** + * @file system.c + * @brief CMSIS Device System Source File for + * NXP LPC80xm Device Series + * @version V1.0 + * @date 01. April 2017 + * + ******************************************************************************/ + +//---------------------------------------------------------------------------- +// Important! +// Please configure the desired initial clock setup for your project in: +// $proj_name/inc/chip_setup.h +//---------------------------------------------------------------------------- + + +#include +#include "LPC8xx.h" +#include "swm.h" +#include "syscon.h" +#include "iocon.h" +#include "fro.h" +#include "rom_api.h" +#include "chip_setup.h" + + +//---------------------------------------------------------------------------- +// Validate the the user's selctions +//---------------------------------------------------------------------------- +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +#if (CHECK_RANGE((FRO_FREQ_VAL), 0, 2)) + #error "FRO_FREQ_VAL: Value out of range." +#endif + +#if (CHECK_RSVD((MAINCLKSEL_VAL), ~0x00000003)) + #error "MAINCLKSEL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSAHBCLKDIV_VAL), 0, 255)) + #error "SYSAHBCLKDIV: Value out of range!" +#endif + +#if (CHECK_RANGE(CLKIN_CLK_VAL, 1000000, 25000000)) + #error "CLKIN frequency is out of bounds" +#endif + + + +//---------------------------------------------------------------------------- +// Calculate internal clock node frequency initial values +//---------------------------------------------------------------------------- +#define __LPOSC_CLK (1000000) + +// determine output of the FRO_CLKDIV subsystem +#if FRO_FREQ_VAL == 0 + #define __FRO_OSCOUT (18000000) +#elif FRO_FREQ_VAL == 2 + #define __FRO_OSCOUT (30000000) +#else + #define __FRO_OSCOUT (24000000) +#endif + +#define __FRO_DIVIDERS_OUT (__FRO_OSCOUT / 2) + +#define __FRO_CLK __FRO_DIVIDERS_OUT + +#define __FRO_DIV_CLK (__FRO_CLK / 2) + +// determine external_clk +#define __SYS_OSC_CLK (0) +#define __CLKIN_CLK (CLKIN_CLK_VAL) +#define __EXTERNAL_CLK __CLKIN_CLK + +// determine main_clk +#if MAINCLKSEL_VAL == 0 + #define __MAIN_CLK __FRO_CLK +#elif MAINCLKSEL_VAL == 1 + #define __MAIN_CLK __EXTERNAL_CLK +#elif MAINCLKSEL_VAL == 2 + #define __MAIN_CLK __LPOSC_CLK +#else + #define __MAIN_CLK __FRO_DIV_CLK +#endif + +// determine system_ahb_clk +#define __SYSTEM_AHB_CLK (__MAIN_CLK / SYSAHBCLKDIV_VAL) + + + +//---------------------------------------------------------------------------- +// Function name: SystemInit +// Sets up the initial chip clocking based on MACROs defined in chip_setup.h. +//---------------------------------------------------------------------------- +void SystemInit (void) { + + uint32_t i; + + for (i = 1; i < 1; i++) __NOP(); // To avoid a warning if variable i is unused + + // Enable clocks to IOCON and SWM upon entry, disable them upon exit + LPC_SYSCON->SYSAHBCLKCTRL[0] |= (SWM | IOCON); + + // Step 0. Configure the FRO subsystem (choose the source for clocks fro and fro_div) + #if (FRO_FREQ_VAL == 0) + //temp |= (FRO_18MHZ << FRO_FREQ_SEL); + LPC_PWRD_API->set_fro_frequency(18000); + #elif (FRO_FREQ_VAL == 2) + //temp |= (FRO_30MHZ << FRO_FREQ_SEL); + LPC_PWRD_API->set_fro_frequency(30000); + #else + //temp |= (FRO_24MHZ << FRO_FREQ_SEL); + LPC_PWRD_API->set_fro_frequency(24000); + #endif +//temp = LPC_SYSCON->FROOSCCTRL; // Get the current register contents +//temp &= ~(FRO_FREQSEL_MASK); // Preserve all but the bits of interest [1:0] +///PC_SYSCON->FROOSCCTRL = temp; // Update the actual register +//LPC_SYSCON->FRODIRECTCLKUEN = 0; // Toggle the update register for the output mux +//LPC_SYSCON->FRODIRECTCLKUEN = 1; +//while (!(LPC_SYSCON->FRODIRECTCLKUEN & 1)) __NOP(); // Wait for update to take effect + + // Configure clk_in, if needed for main_clk or other (e.g. clock out, ADC clk.) + #if ((MAINCLKSEL_VAL == 1) || (EXT_CLOCK_FORCE_ENABLE == 1)) + LPC_IOCON->PIO0_1 &= (IOCON_MODE_MASK | MODE_INACTIVE); // Disable pull-up and pull-down + LPC_SWM->PINENABLE0 &= ~(CLKIN); // Enable CLKIN func. + #endif + + // Step 2. Power up the LP OSC if it's needed for main_clk + #if (MAINCLKSEL_VAL == 2) + LPC_SYSCON->PDRUNCFG &= ~(LPOSC_PD); // Power up the LP OSC + for (i = 0; i < 200; i++) __NOP(); // Wait for osc to stabilize + #endif + + // Step 4. Choose source for main_clk + LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_VAL; // Update the actual register + LPC_SYSCON->MAINCLKUEN = 0; // Toggle update register + LPC_SYSCON->MAINCLKUEN = 1; + while (!(LPC_SYSCON->MAINCLKUEN & 1)) __NOP(); // Wait until updated + + // Step 6. Configure the main_clock divider + LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_VAL; // Update the actual register + + LPC_SYSCON->SYSAHBCLKCTRL[0] &= ~(SWM | IOCON); // Turn off peripheral clocks before leaving + +} // end of SystemInit + + + + +//---------------------------------------------------------------------------- +// Global clock variable declarations and initial value assignments +//---------------------------------------------------------------------------- +uint32_t main_clk = __MAIN_CLK; +uint32_t lposc_clk = __LPOSC_CLK; +uint32_t fro_clk = __FRO_CLK; +uint32_t fro_div_clk = __FRO_DIV_CLK; +uint32_t system_ahb_clk = __SYSTEM_AHB_CLK; + +//---------------------------------------------------------------------------- +// Function name: SystemCoreClockUpdate +// Determines the actual system_ahb_clk (core clock), main_clock, +// fro_clk, and fro_div_clk frequencies +// based on the current state of the device, and updates the associated +// global clock variables. +//---------------------------------------------------------------------------- +void SystemCoreClockUpdate (void) +{ + uint32_t external_clk; + uint32_t fro_oscout, fro_clock; + uint32_t temp; + + // Set the fro_clk and fro_div_clk variables according to current register settings + temp = LPC_SYSCON->FROOSCCTRL; + switch (temp & FRO_FREQSEL_MASK) { + case 0: fro_oscout = 18000000; break; + case 1: fro_oscout = 24000000; break; + default:fro_oscout = 30000000; break; + } + fro_clock = 0; + if ((LPC_SYSCON->PDRUNCFG & (FROOUT_PD | FRO_PD)) == 0x0) { + fro_clock = fro_oscout; + } + fro_clk = fro_clock / 2; + fro_div_clk = fro_clk / 2; + + // Set the external_clk variable according to current register values +//if (LPC_SYSCON->EXTCLKSEL == 0) +// external_clk = __SYS_OSC_CLK; +//else + external_clk = __CLKIN_CLK; + + // Set the lposc_clk variable + if (!(LPC_SYSCON->PDRUNCFG & LPOSC_PD)) { + lposc_clk = __LPOSC_CLK; + } + else { + lposc_clk = 0; + } + + // Set the main_clk variable according to current register values + switch (LPC_SYSCON->MAINCLKSEL & 0x3) { + case 0: main_clk = fro_clk; break; + case 1: main_clk = external_clk; break; + case 2: main_clk = lposc_clk; break; + case 3: main_clk = fro_div_clk; break; + } + + // Set the system_ahb_clk (a.k.a SystemCoreClock) variable according to current register values + system_ahb_clk = main_clk / LPC_SYSCON->SYSAHBCLKDIV; + +} // end of SystemCoreClockUpdate